Functional Description - STMicroelectronics SPC572L series Reference Manual

RM0400
Safety Latent: The register bits/fields in this category should be protected by LBIST at chip
level. The following register bits/fields are classified in this category:
•
DSPI Status Register (DSPI_SR) [0:15] (for stuck at 0)
•
DSPI Status Register Extended (DSPI_SREX) [0:8] (for stuck at 0)
•
DSPI DSI Deserialized Data Interrupt Mask Register 0 (DSPI_DIMR0)
•
DSPI DSI Deserialized Data Interrupt Mask Register 1 (DSPI_DIMR1)
•
DSPI DSI Deserialized Data Polarity Interrupt Register 0 (DSPI_DPIR0)
•
DSPI DSI Deserialized Data Polarity Interrupt Register 1 (DSPI_DPIR1)
Non-Safety: All other registers and bits fall in this category.
46.5

Functional description

The Deserial Serial Peripheral Interface (DSPI) block supports full-duplex, synchronous
serial communications between MCUs and peripheral devices. The DSPI can also be used
to reduce the number of pins required for I/O by serializing and deserializing up to 64
parallel input/output signals. All communications are done with SPI-like protocol.
The DSPI has the following configurations:
•
SPI Configuration in which the DSPI operates as a basic SPI or a queued SPI.
•
DSI Configuration in which the DSPI serializes and deserializes Parallel Input/Output
signals or bits from memory-mapped register.
•
CSI Configuration in which the DSPI combines the functionality of the SPI and DSI
configurations.
The DCONF field in the DSPI Module Configuration Register (MCR) determines the DSPI
Configuration. See
the DSPI configuration values.
The CTARn registers hold clock and transfer attributes. The SPI configuration allows CTAR
selection on a frame by frame basis by setting a field in the SPI command. Extended SPI
Mode (DSPI_MCR[XSPI]) further allows the usage of CTAREn (CTARn Extended) registers
to send multiple Data frames (of up to 32-bit frame size) using a single Command frame.
DSI configuration statically selects which CTAR to use. In CSI, Configuration priority logic
determines if SPI data or DSI data is transferred and dictates which CTAR is used for the
data transfer.
See DSPI Clock and Transfer Attributes Registers for information on the fields of the
CTARs.
See DSPI Clock and Transfer Attributes Registers Extended for information on the fields of
the CTARE registers.
Typical master to slave connections are shown in
When a data transfer operation is performed, data is serially shifted a predetermined
number of bit positions. Because the modules are linked, data is exchanged between the
master and the slave: the data that was in the master shift register is now in the shift register
of the slave, and vice versa.
At the end of a transfer, the TCF bit in the Status Register is set to indicate a completed
transfer.
Section 46.3.1: DSPI Module Configuration Register (DSPI_MCR)
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Deserial Serial Peripheral Interface (DSPI)
Figure 613.
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