Table 612. Dspi_Ctarn Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Deserial Serial Peripheral Interface (DSPI)
Field
Double Baud Rate. (Master mode only)
Doubles the baud rate of the Serial Communications Clock (SCK). It halves the Baud Rate
division ratio, supporting faster frequencies and odd division ratios for the Serial Communications
Clock (SCK).
0 When DBR is set, the duty cycle of the Serial Communications Clock (SCK) depends on the
value in the Baud Rate Prescaler and the Clock Phase bit as listed in
DBR
See the BR field description in this table for details on how to compute the baud rate.
Refer to
0 The baud rate is computed normally with a 50/50 duty cycle.
1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
Frame Size
The number of bits transferred per frame is equal to the FMSZ field value plus 1. The minimum
valid value for the number of bits to be transmitted for any mode is 4.There is a constraint on the
minimum allowable Frame size, which depends on the Register Read/Write clock to the Protocol
Clock Ratio. The minimum Frame size (FMSZ + 1) is decided by the following equation. Upper
Ceiling must be applied for non-integer values.
Min. Frame Size = ( (4 x f
f = Protocol Clock Frequency
p
f = Register Read/Write Clock Frequency
r
1–4
n = Multiple of protocol clock required to get Baud Clock - Given by (PBR x BR) / (1 + DBR)
FMSZ
The minimum frame size can never be less than 4. There is no constraint on the maximum
programmable frame size.
Note that 'f
When the DSPI operates in TSB mode, the FMSZ field value plus 1 is equal to the data frame bit
number, where control of the PCS assertion switches from the DSICR0 to the DSICR1 register. If
TSB Mode is operated when DSI is used in 64-bit mode, then DSICR0[FMSZ4] also comes into
picture while switching PCS assertion control.
Clock Polarity. (Master and Slave mode)
Selects the inactive state of the Serial Communications Clock (SCK).
Devices must have identical clock polarities for successful communication between serial
devices.
5
When the Continuous Selection Format is selected, switching between clock polarities without
CPOL
stopping the DSPI can cause errors in the transfer due to the peripheral device interpreting the
switch of clock polarity as a valid clock edge.
0 The inactive state value of SCK is low.
1 The inactive state value of SCK is high.
Clock Phase or TSB mode. (Master and Slave mode)
Selects which edge of SCK causes data to change and which edge causes data to be captured.
Devices must have identical clock phase settings for successful communication between serial
6
devices.
CPHA
In Continuous SCK or TSB modes, this bit is ignored and the transfers are done as if the CPHA
bit is set to 1.
0 Data is captured on the leading edge of SCK and changed on the following edge.
1 Data is changed on the leading edge of SCK and captured on the following edge.
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Table 612. DSPI_CTARn field descriptions

Table 613 for DSPI SCK duty cycle values.
) + (3 x f
p
' can be equal to, less than or greater than 'f
p
DocID027809 Rev 4
Description
) ) / (n x f )
r r
' purely based on user requirement.
r
RM0400
Table 613.