Peripheral Bridge; Introduction; Features; General Operation - STMicroelectronics SPC572L series Reference Manual

Peripheral Bridge

15 Peripheral Bridge
15.1

Introduction

The peripheral bridge converts the crossbar switch interface to an interface that can access
a majority of peripherals on the device.
The peripheral bridge occupies a 64 MB portion of the address space. (Not all peripheral
slots may be used. See
details on slot assignment.) The bridge includes separate clock enable inputs for each of the
slots, to accommodate slower peripherals.
15.1.1

Features

Key features of the peripheral bridge are:
•
Supports a pair of 32-bit transactions for selected 64-bit memory accesses
•
Each independently configurable peripheral includes a clock enable, which allows
peripherals to operate at any speed less than the system clock rate
•
Programming model that provides memory protection functionality
15.1.2

General operation

The slave devices connected to the peripheral bridge are modules that contain
readable/writable control and status registers. The system masters read and write these
registers through the peripheral bridge. The peripheral bridge generates module enables,
the module address, transfer attributes, byte enables, and write data as inputs to the
peripherals. The peripheral bridge captures read data from the peripheral interface and
drives it to the crossbar switch.
Each peripheral is typically allocated one 16-KB block (or slot) of the memory map. Usually,
the peripheral bridge uses the size of the addressed peripheral to perform proper data byte
lane routing only; no bus decomposition (dynamic bus sizing) is performed. However, there
are the following exceptions:
•
Aligned 64-bit reads are permitted to 32-bit slots.
•
Aligned 64-bit writes may be targeted to 32-bit slots.
•
Aligned or misaligned 64-bit instruction fetches may also be performed to 32-bit slots.
All other 64-bit accesses result in an error response.
15.2

Memory map and register definition

Offset
address
0x000 Master Privilege Register A (AIPS_MPRA)
0x004
0x100 Peripheral Access Control Register A (AIPS_PACRA)
318/2058
Chapter 6: Device configuration
Table 135. Peripheral bridge memory map
Register
Reserved
DocID027809 Rev 4
or Chapter 5: Memory map
Width
(bits)
32
—
32
RM0400
for
Location
on page 319
—
on page 320