Adjustment For Variation In Sensor (Tx) Clock - STMicroelectronics SPC572L series Reference Manual

SENT Receiver (SRX)
49.4.4.2 Slow message buffers
Overflow in Slow Message buffers can occur when the CPU or DMA does not read
messages from that channel for a long period of time. The receiver channel stores two
messages in its buffers and indicates an overflow when these buffers are full.
When an overflow event occurs, further reception of slow messages is halted until the
buffers are read out by CPU or DMA. Since it is less likely that CPU or DMA do not read the
read registers for 32 or 36 fast message length duration, an overflow in slow messages
would not be as frequent as in fast messages.
49.4.5

Adjustment for variation in sensor (Tx) clock

The clock used by the Channel Receiver (referred to as Receiver Clock, or Rx_CLK) to
sample the message nibbles is generated from a High Frequency Receiver Clock or
Protocol Clock. This high frequency receiver clock is divided using a prescaler counter
which generates a tick when it rollovers on reaching a count equal to the Prescaler Value
programmed in the channel's clock control register. The receive clock is generated
separately for each channel. By varying this Prescaler Factor, we can control the period of
the receive clock and make it close to the Transmitter clock used by the sensor for the
particular channel.
After reset and once channel is enabled, the compensated prescaler value is set to Zero
and the user software programs the Prescaler Value to obtain the desired receiver clock
frequency for the particular channel. Thus, the receiver starts working by assuming that the
transmitter is sending messages on the frequency that is programmed in its channel clock
control register. The channel's input after filtering is continuously measured by the Prescaler
Counter. The compensation logic checks each pulse length and determines the calibration
pulse from them. When a calibration pulse is detected, the compensated prescaler value is
computed and stored in the Channel's Clock Control Register
'n' Clock Control Register (n = 0 to (CH-1))
to determine the variation in Tx Clock.
Note: A pause pulse may incidentally be detected as a synchronization/calibration pulse during
start up after reset. The correction value would be computed on the pause pulse too but
since the next synchronization pulse would follow, the logic would again detect the falling
edge on the synchronization pulse and the correction value would now be correctly
computed on the correct synchronization pulse.
The Clock Compensation or Correction happens for every messages that is received and
the compensated prescaler value remains constant for that message.
49.4.5.1 Adjustment for nibble length variation
Section 6.2 of SAE Specifications specifies the maximum allowable limits for clock drift and
jitter for the transmitter and receiver separately. This can cause the length of nibbles to vary
and can cause incorrect sampling of data nibbles. This variation is adjusted by the SENT
Receiver when nibbles are being sampled.
49.4.6 Input programmable filter
The Input Programmable Filter ensures that only valid input pin transitions are received by
the SENT Receiver module. The input programmable filter is an 8-bit programmable up
counter that increments on the high frequency receiver clock. The sensor input signal from
device's pad is synchronized by high frequency receiver clock. When a state change occurs
1404/2058
(CHn_CLK_CTRL)). Software can use this value
DocID027809 Rev 4
RM0400
(Section 49.3.2.18: Channel