Table 240. Pcs Divider Change Register 3 (Cgm_Pcs_Divc3) Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Clock Generation Module (MC_CGM)
24.3.1.8 PCS Divider Change Register 3 (CGM_PCS_DIVC3)
This register defines the rate of frequency change and initial change value for the progressive system
clock switching when switching the system clock source to or from the PLL0 PHI1 on ramp-up and ramp-
down, respectively. See
these values.
Note: Byte write accesses are not allowed for the INIT field of this register. Such accesses do not
result in an exception, but the value is not loaded with the new value.
Address 0x071C
0 1 2
R
W
Reset 0 0 0
16 17 18
R 0 0 0
W
Reset 0 0 0
Figure 188. PCS Divider Change Register 3 (CGM_PCS_DIVC3)

Table 240. PCS Divider Change Register 3 (CGM_PCS_DIVC3) field descriptions

Field
0–15 Divider Change Initial Value — This is initial change value of the clock divider for the clock ramp-up
phase when switching to the reserved.
INIT
16–23 Reserved
24–31 Divider Change Rate — This value controls the change value of the clock divider for the clock ramp-up
and ramp-down phase when switching to/from the reserved.
RATE
24.3.1.9 PCS Divider Start Register 3 (CGM_PCS_DIVS3)
This register defines the initial division value for the progressive system clock switching when switching
the system clock source to the PLL0 PHI1 on ramp-up. See
Switching for details on how to set this value.
Note: Byte and half-word write accesses are not allowed for this register. Such accesses do not
result in an exception, but the value is not loaded with the new value.
504/2058
Section 24.4.1.2, Progressive System Clock Switching
Access: User read/write, Supervisor Supervisor read/write, Test read/write
3 4 5 6
0 0 0 1
19 20 21 22
0 0 0 0
0 0 0 0
DocID027809 Rev 4
7 8 9 10
INIT
1 1 1 1
23 24 25 26
0
0 0 0 0
Description
Section 24.4.1.2, Progressive System Clock
RM0400
for details on how to set
11 12 13 14
0 0 1 1
27 28 29 30
RATE
0 0 0 0
15
1
31
0