Edma Basic Data Flow - STMicroelectronics SPC572L series Reference Manual

Enhanced Direct Memory Access (eDMA)
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Transfer control descriptor memory
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19.4.2

eDMA basic data flow

The basic flow of a data transfer can be partitioned into three segments. As shown in
Figure 151, the first segment involves the channel activation. In the diagram, this example
uses the assertion of the eDMA peripheral request signal to request service for channel n.
Channel activation via software and the TCDn_CSR[START] bit follows the same basic flow
as peripheral requests. The eDMA request input signal is registered internally and then
routed through the eDMA engine: first through the control module, then into the program
model and channel arbitration. In the next cycle, channel arbitration is performed, using the
fixed-priority or round-robin algorithm. After arbitration is complete, the activated channel
number is sent through the address path and converted into the address to access the local
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start and into channel y registers for a preemption start. After the minor loop
completes execution, the address path hardware writes the new values for the
TCDn _{SADDR, DADDR, CITER} back to local memory. If the major iteration
count is exhausted, additional processing is performed, including updates to the
final address pointer, reloading the TCDn _CITER field, and a possible fetch of the
next TCDn from memory as part of a scatter/gather operation.
Data path:
This block implements the bus master read/write datapath. It includes 32 bytes of
register storage and the necessary multiplex logic to support any data alignment.
The internal read data bus is the primary input, and the internal write data bus is
the primary output.
The address and data path modules directly support the two-stage pipelined
internal bus. The address path module represents the first stage of the bus
pipeline (address phase), while the data path module implements the second
stage of the pipeline (data phase).
Program model/channel arbitration:
This block implements the first section of the eDMA programming model as well
as the channel arbitration logic. The programming model registers are connected
to the internal peripheral bus (not shown). The eDMA peripheral request inputs
and interrupt request outputs are also connected to this block (via control logic).
Control:
This block provides all the control functions for the eDMA engine. For data
transfers where the source and destination sizes are equal, the eDMA engine
performs a series of source read/destination write operations until the number of
bytes specified in the minor loop byte count has moved. For descriptors where the
sizes are not equal, multiple accesses of the smaller size data are required for
each reference of the larger size. As an example, if the source size references 16-
bit data and the destination is 32-bit data, two reads are performed, then one 32-
bit write.
Memory controller:
This logic implements the dual-ported controller, managing accesses from the
eDMA engine as well as references from the internal peripheral bus.
As noted earlier, in the event of simultaneous accesses, the eDMA engine is given
priority and the peripheral transaction is stalled.
Memory array:
TCD storage is implemented using a single-port, synchronous RAM array.
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