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GTM Development Interface (GTMDI)
Register index: 44
31
30
R
0
0
W
RESET:
0
0
15
14
R
0
0
W
RESET:
0
0
Figure 422. DPLL watchpoint control 4 register (GTMDI_DPLL_WPC4)
Table 475
Field
11–0
RAM_ADDR_MASK
42.5.1.18 DPLL watchpoint control 5 register (GTMDI_DPLL_WPC5)
The GTMDI_DPLL_WPC5 register shown in
monitored during DPLL selected RAM access. Once this address value matches with the
DPLL RAM address a Watchpoint is issued.
Register index: 45
31
30
R
0
0
W
RESET:
0
0
15
14
R
0
0
W
RESET:
0
0
Figure 423. DPLL watchpoint control 5 register (GTMDI_DPLL_WPC5)
Table 476
910/2058
29
28
27
26
0
0
0
0
0
0
0
0
13
12
11
10
0
0
0
0
0
0
describes the GTMDI_DPLL_WPC4 register functions.
Table 475. GTMDI_DPLL_WPC4 field descriptions
RAM Address mask. The RAM_ADDR_MASK[11:0] field is a mask applied bit by bit to
the RAM_ADDR defined in the GTMDI_DPLL_WPC5 register. If mask is 1, the
corresponding RAM_ADDR bit is not valid for comparison, thus it always returns a match
when compared to the selected RAM address.
29
28
27
26
0
0
0
0
0
0
0
0
13
12
11
10
0
0
0
0
0
0
describes the GTMDI_DPLL_WPC5 register functions.
DocID027809 Rev 4
25
24
23
22
0
0
0
0
0
0
0
0
9
8
7
6
RAM_ADDR_MASK
0
0
0
0
Description
Figure 423
25
24
23
22
0
0
0
0
0
0
0
0
9
8
7
6
RAM_ADDR
0
0
0
0
21
20
19
18
0
0
0
0
0
0
0
0
5
4
3
2
0
0
0
0
defines the address value that is
21
20
19
18
0
0
0
0
0
0
0
0
5
4
3
2
0
0
0
0
RM0400
17
16
0
0
0
0
1
0
0
0
17
16
0
0
0
0
1
0
0
0
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