Table 602. Sipi_Mcr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Offset: 009Ch
0 1
R
Rese
rved
W
Reset 0 0
16 17
R
1
AID
W
Reset 0 0
1
Can be written in initialization mode only (SIPI_MCR[INIT] = 1).
2
Can only be written when SIPI_MCR[MOEN] = 1.
3
Can be written only once after reset.
Figure 576. SIPI Module Configuration Register (SIPI_MCR)
Field
Freeze Enable
The FRZ bit specifies the SIPI behavior when Debug mode is requested at the MCU level. When
0
FRZ is asserted, the SIPI is enabled to enter Freeze mode. Negation of this bit field causes SIPI to
exit Freeze mode.
FRZ
0 Not enabled to enter Freeze mode
1 Enabled to enter Freeze mode
1 Reserved
Halt Mode Enable. Assertion of this bit puts SIPI into Freeze mode. No Rx or Tx is performed in the
SIPI until this bit is cleared. If this bit is enabled in during Tx or Rx communications, the current
2
activity will finish, then the SIPI will enter Freeze mode.
HALT
0 No Freeze mode request
1 Enters Freeze mode if FRZ bit is asserted.
3–4 Reserved
These bits should be programmed by software in initialization mode, SIPI_MCR[INIT] = 1, writes
during other times are ignored. The timeout counter runs on the prescaled system clock. Default
value is 64 (040h). The allowed programmable values are:
040h 64
5–15
080h 128
PRSCLR
100h 256
200h 512
400h 1024
2 3 4 5
0 0
0 0 0 0
18 19 20 21
0 0 0
0 0 0 0

Table 602. SIPI_MCR field descriptions

DocID027809 Rev 4
Serial Interprocessor Interface (SIPI)
6 7 8 9
PRSCLR
0 0 0 1
22 23 24 25
0 0 0
0 0 0 0
Description
Access: User read/write
10 11 12 13
1
0 0 0 0
26 27 28 29
0
0 0 0 0
14 15
0 0
30 31
0 0
1127/2058
1133