Table 1022. L2Nsel3 Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Sequence Processing Unit (SPU)
The L2nSEL3 register fields are described in
Field
Fourth AND Gate Input1 Selection.
000000No Input is selected (tie to 1'b1)
000001Level1 MUX 0 output
5–0
000010Level1 MUX 1 output
FourthANDInput1 000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
7–6 Reserved. Read returns 0.
Fourth AND Gate Input 2 Selection.
000000No Input is selected (tie to 1'b1)
000001Level1 MUX 0 output
13–8
000010Level1 MUX 1 output
FourthANDInput2 000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
15–14 Reserved. Read returns 0.
Fourth AND Gate Input 3 Selection.
000000No Input is selected (tie to 1'b1)
000001Level1 MUX 0 output
21–16
000010Level1 MUX 1 output
FourthANDInput3 000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
23–22 Reserved. Read returns 0.
Fourth AND Gate Input 4 Selection.
000000No Input is selected (tie to 1'b1)
000001Level1 MUX 0 output
29–24
000010Level1 MUX 1 output
FourthANDInput4 000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
31–30 Reserved. Read returns 0.
63.5.1.3 Sequence unit registers
63.5.1.3.1 Input/output Inversion control state n (IOICn)
An input control register is provided for each event generated by the SLU. This register is
programmed to specify how the input signals to each SLU are combined to generate the
resulting event for that particular sequence. In total, there are 16 inputs for each state and
only one (the first) of the inputs can be used with or without inversion. The input can be left
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Table 1022. L2nSEL3 register field descriptions

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Table 1022.
Description
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