Table 1054. Nar_Tbahi Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Nexus Aurora Router (NAR)
Register index: 5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 1116. Trace memory base address register NAR_TBAHI
Register index: 4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 1117. Trace memory base address register NAR_TBALO
The NAR_TBALO and NAR_TBAHI registers are described in the following tables.
Field
31–0
TBAHI
Field
31–10
TBALO
9
ADRLO[9]
8
ADRLO[8]
7
ADRLO[7]
6
ADRLO[6]
5–0
65.4.3.2 Trace memory bus control register (NAR_TCR)
The trace memory bus control register is used to control the attributes of the trace memory
bus port, such as block transfer size and message priority. Since the trace memory bus
transfers are expected to go to a static block of external memory, a maximum transfer size
must be specified to prevent the NAR from overwriting memory it is not authorized to
access. This is done via the MXFR max transfer size register field. The memory allocation is
1882/2058
TBALO

Table 1054. NAR_TBAHI field descriptions

Trace Debug Memory Base Address on AHB-EW port, upper part. For 32-bit address
applications this field is all zeros.
Table 1055. NAR_TBALO field descriptions
Trace Debug Memory Base Address on AHB-EW port, lower part
Base Address LSB for BTS = 11
(384-byte block)
Base Address LSB for BTS = 10
(256-byte block)
Base Address LSB for BTS = 01
(128-byte block)
Base Address LSB for BTS = 00
(64-byte block)
Reserved
DocID027809 Rev 4
TBAHI
9
ADR
LO[9]
0
Description
Description
RM0400
8 7 6 5 4 3 2 1 0
8 7 6 5 4 3 2 1 0
ADR ADR ADR
0 0 0 0 0 0
LO[8] LO[7] LO[6]
0 0 0 0 0 0 0 0 0