Stop Mode Description - STMicroelectronics SPC572L series Reference Manual

GTM101 Integration (GTMINT) Module
43.3.3.2 Error Report Description
Each RAM generates a defined number of information to report an error on an access. Each
of them is described below.
•
Error Address – this is the mapped address of the RAM as defined in
Module memory
by the two error signals below. It is reported on read or write operations.
• Non-correctable Error – This one bit width error indicates that:
–
•
Correctable Error – this one bit width error indicates that:
–
This Error Report remains active for only one RAM clock cycle and should be captured by
the external RAM Error Monitor module. These error indications are also available for the
GTM-IP timer module that is the block that requests the RAM accesses. Uncorrectable ECC
error indication are provided to GTM-IP but the reaction to the error depends on this block
itself. Please refer to its specification for more details.
43.3.4

Stop Mode Description

The stop mode is characterized by the stopping of the functional clock and the timer
configuration registers clock. Therefore, the timers become stopped and almost all registers
access are not allowed. This mode can be requested by two ways:
•
By asserting field GTMMCR[MDIS].
•
By receiving the SoC stop request signal ipg_stop.
–
However, it is important to note that to confirm the stop request was granted, it is necessary
to read the stop status field GTMMCR[STPS].
43.3.4.1 Stop Mode by MDIS
The stop mode is requested by asserting this bit field with a write operation on the
GTMMCR mapped register. The module only requests to stop the clocks when no slave bus
accesses are pending in the GTM-IP. When in stop mode:
• The clocks are disabled to feed the whole GTM-IP and peripheral functions like the
ECC
•
The stop status field GTMMCR[STPS] is set.
•
Read or write accesses to all mapped registers are not allowed and generates an
access error indication, except accesses for the GTMMCR.
•
The slave bus clock is not affected by stop mode.
This stop mode ends by clearing GTMMCR[MDIS]. GTMMCR[STPS] is automatically
cleared (it is considered that the SoC stop request is not set).
992/2058
map. This field has only meaning when an error occurs and is flagged
The ECC detected errors in the read access and it is not possible to correct them
because the ECC can only fix single bit errors. The error can occur in the RAM
read data bus (parity bits + data) or in the address value that the RAM has
received.
The ECC detected and corrected a single bit error on the RAM read data bus
(parity bits + data). The parity bits are discarded after the ECC decoder but this
error report includes these bits to obtain the performance of the whole RAM data
storage sector.
the minimum waiting time to a new stop request is about 20 bus clock cycles.
DocID027809 Rev 4
RM0400
Section 43.2.1,