Dspi Configurations - STMicroelectronics SPC572L series Reference Manual

Deserial Serial Peripheral Interface (DSPI)
The DSPI also supports pin reduction through serialization and deserialization if enabled for
the module.
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Two sources of serialized data:
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Deserialized data provided as:
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Interrupt conditions:
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Transfer initiation conditions:
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Pin serialization/deserialization with interleaved SPI frames for control and diagnostics.
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Continuous serial communications clock.
DSPI supports a combination of SPI and DSI modes of operation (Combined Serial
Interface (CSI)) for the downstream Micro Second Channel in either Timed Serial Bus (TSB)
configuration or Interleaved Frames Configuration (configurable by software). Both TSB and
Interleaved TSB modes have the following common features:
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Transmission of frames is performed at frame boundaries.
• Frames from SPI and DSI are identifiable by a bit transmitted at the start of each frame.
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Separate interrupts for frame completion from SPI and DSI.
46.1.3

DSPI configurations

The DSPI module can operate in three configurations: SPI, DSI, and CSI. See the relevant
section in the 'Communication interfaces' section of the 'Device Configuration' chapter.
46.1.3.1 SPI configuration
The SPI configuration allows the DSPI to send and receive serial data. This configuration
allows the DSPI to operate as a basic SPI block with internal FIFOs supporting external
queues operation. Transmit data and received data reside in separate FIFOs. The host CPU
or a DMA controller read the received data from the receive FIFO and write transmit data to
the transmit FIFO.
For queued operations, the SPI queues can reside in system RAM which is external to the
DSPI. Data transfers between the queues and the DSPI FIFOs are accomplished by a DMA
controller or host CPU.
queues in system RAM.
1136/2058
DSPI memory-mapped register
parallel input signals
programmable selection of source data on bit basis.
parallel Output signals
bits in a memory-mapped register
deserialized data matches pre-programmed pattern (DDIF)
transfer of current DSI frame complete (DSITCF)
DSI parity error (DPEF)
continuous
change in data
Figure 583
DocID027809 Rev 4
shows a system example with DMA, DSPI and external
RM0400