Table 659. Tmcr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
Field
0-5 Reserved
Clock Test mode. S/W can define when the clock test mode is enabled. This bit can also be set and
cleared by LFAST slave H/W on reception of an ICLC command.
6
1Clock Test mode enabled
CLKTST
0Clock Test mode disabled
Loopback mode Logic Enable. S/W can define when the loopback logic is enabled. This bit can also
be written by LFAST slave H/W on reception of an ICLC command.
7
1Loopback mode is enabled
LPON
0Loopback mode is disabled
8-12 Reserved
Loopback mode. Defines the type of loopback mode enabled.
000 Rx loopback
001 Rx LVDS loopback
13-15
010 Tx loopback without automatic frame generation
LPMOD
011 Tx loopback with automatic frame generation
100 Tx LVDS loopback (external) with automatic frame generation
Others - Reserved (should not be written by S/W)
Loopback check mode valid pass frames threshold value. Defines the number of frames to verify
before setting GCR[LPFPDV] when running in Automatic Loopback Frame mode. The loopback
frame is considered pass when the payload is CBh, header is 13h and sync is valid. This mode is
valid only when TMCR[LPMOD] = 011b or TMCR[LPMOD] = 100b.
0000h Reserved.(Not to be used)
16-31
0001h Check 1 frame have correct sync, header and payload.
LPFRMTH
...
FFFEh Check 65534 frames have correct sync, header and payload.
FFFFh Check 65535 frames have correct sync, header and payload.
47.6.2.5 Auto Loopback Control Register (ALCR)
Offset:
0010h
0 1
R 0 0
W
Reset 0 0
16 17
R
W
Reset 0 0
1
Writable only when TMCR[LPON] = 0.

Table 659. TMCR field descriptions

2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
Figure 645. Auto Loopback Control Register (ALCR)
DocID027809 Rev 4
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
1
LPFMCNT
0 0 0 0
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
14 15
0
0 0
30 31
0 0
1233/2058
1292