Table 152. Overlapping Region Descriptor Example - STMicroelectronics SPC572L series Reference Manual

RM0400
maintenance of the valid bit, so if this approach is followed, there are no coherency
issues with the multi-cycle descriptor writes.
•
Modifying a region descriptor—Load the updates into the region descriptor using
sequential 32-bit writes. Writing to Word3 re-enables the region descriptor valid bit. The
hardware assists in the maintenance of the valid bit, so if this approach is followed,
there are no coherency issues with the multi-cycle descriptor writes.
•
Removing a region descriptor—Clearing RGDn_Word3[VLD] deletes an existing region
descriptor.
•
Accessing the SMPU—Allocate a region descriptor to restrict SMPU access to
supervisor mode from a specific master.
•
Detecting an access error—The current bus cycle is terminated with an error response
and EARn and EDRn capture information on the faulting reference. The error-
terminated bus cycle typically initiates an error response in the originating bus master.
For example, a processor core may respond with a bus error exception, while a data
movement bus master may respond with an error interrupt. The processor can retrieve
the captured error address and detail information simply by reading E{A,D}Rn.
CESR0[MERR] signals. The error registers contain the captured fault data.
•
Overlapping region descriptors—Applying overlapping regions often reduces the
number of descriptors required for a given set of access controls. In the overlapping
memory space, the protection rights of the corresponding region descriptors are
logically summed together (the boolean OR operator).
The following dual-core system example contains four bus masters: the two processors
(CP0, CP1) and two DMA engines (DMA1, a traditional data movement engine transferring
data between RAM and peripherals, and DMA2, a second engine transferring data to/from
the RAM only). Consider the following region descriptor assignments:
Region description
CP0 code
CP1 code
CP0 data & stack
CP0 → CP1 shared data
CP1 → CP0 shared data
CP1 data & stack
Shared DMA data
SMPU
Peripherals
In this example, there are eight descriptors used to span nine regions in the three main
spaces of the system memory map (flash, RAM, and peripheral space). Each region
indicates the specific permissions for each of the four bus masters, and this definition
provides an assigned set of shared, private, and executable memory spaces.
Of particular interest are the two overlapping spaces: region descriptors 2 & 3 and 3 & 4.

Table 152. Overlapping region descriptor example

RGDn CP0
0 rwx
1 r--
2 rw-
2
3 r--
4
4 —
5 rw-
6 rw-
7 rw-
DocID027809 Rev 4
System Memory Protection Unit (SMPU)
CP1 DMA1
r-- —
rwx —
— —
r-- —
rw- —
rw- rw
rw- —
rw- rw
System memory
DMA2
map space
—
Flash
—
—
—
RAM
—
rw
—
Peripheral space
—
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