Fifo Receive Bound Register (Frbr) - STMicroelectronics SPC572L series Reference Manual

RM0400
Offset: 144h
0 1 2 3
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
Number of bytes written to transmit FIFO before transmission of a frame begins
00 64 bytes written
TFWR
01 64 bytes written
10 128 bytes written
11 192 bytes written
48.4.19

FIFO Receive Bound Register (FRBR)

FRBR indicates the upper address bound of the FIFO RAM. Drivers can use this value,
along with the FRSR, to appropriately divide the available FIFO RAM between the transmit
and receive data paths.
Offset: 14Ch
0 1 2 3
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Field
R_BOUND Highest valid FIFO RAM address.
48.4.20 FIFO Receive Start Register (FRSR)
FRSR indicates the starting address of the receive FIFO. FRSR marks the boundary
between the transmit and receive FIFOs. The transmit FIFO uses addresses from the start
of the FIFO to the location four bytes before the address programmed into the FRSR. The
receive FIFO uses addresses from FRSR to FRBR inclusive.
Hardware initializes the FRSR at reset. FRSR only needs to be written to change the default
value.
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 707. Transmit FIFO Watermark Register (TFWR)
Table 717. TFWR field descriptions
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 708. FIFO Receive Bound Register (FRBR)
Table 718. FRBR field descriptions
DocID027809 Rev 4
Fast Ethernet Controller (FEC)
Description
Description
Access: User read/write
Access: User read
R_BOUND 0 0
0
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1358