Dma Controller Configuration - STMicroelectronics SPC572L series Reference Manual

Device configuration
Key for CPU Pipeline Stages Key for CPU Pipeline Stages
IF IF Instruction Fetch Instruction Fetch
D/EA D/EA Decode/Effective address calculation Decode/Effective address calculation
E/M E/M Execute/Memory Access Execute/Memory Access
W W Wait state Wait state
S S Stall Stall
WB WB Writeback Writeback
IRQ signalled to IRQ signalled to
INTC INTC
dual single cycle instructions dual single cycle instructions
dual single cycle instructions dual single cycle instructions
dual single cycle instructions dual single cycle instructions
EXINT EXINT
INTC INTC
cycle cycle
6.3.7

DMA controller configuration

This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module's dedicated chapter in the
device reference manual.
146/2058
Figure 10. Interrupt timing
IRQ signalled to Core IRQ signalled to Core
Final Sample Point Final Sample Point
IF IF D/EA D/EA E/M0 E/M0 E/M1 E/M1
IF IF D/EA D/EA abort abort
IF IF
4 4 8 8 12 12 13 13 14 14
Figure 11. DMA controller configuration
Transfers
DocID027809 Rev 4
WB WB
S S S S S S
e_stwu e_stwu IF IF D/EA D/EA
e_stmvsrrw e_stmvsrrw
wrteei wrteei
15 15 16 16 17 17
Peripheral
bridge
Register
access
DMA controller
E/M0 E/M0 E/M1 E/M1 WB WB
IF IF D/EA D/EA E/M0 E/M0 E/M1 E/M1 WB WB
IF IF D/EA D/EA E/M0 E/M0 E/M1 E/M1
18 18 19 19 20 20 21 21
Requests
RM0400
MSR[EE] MSR[EE]
= 1 = 1
WB WB
22 22 23 23 24 24