Table 624. Dspi_Dsicr0 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
MSB of the frame size in master mode when DSI is used in 32-bit mode.
1
If the bit is set, 16 is added to the frame size, as defined by the CTARn[FMSZ] field.
FMSZ4
The CTARx register is selected by the DSICTAS field.
MSB of the frame size in master mode when DSI is used in 64-bit mode.
If the bit is set, 32 is added to the frame size, as defined by the concatenation of
8
{DSICR0[FMSZ4], CTARn[FMSZ]} fields. The CTARx register is selected by the DSICTAS field.
Hence the final concatenated frame size using this bit is {DSICR0[FMSZ5], DSICR0[FMSZ4],
FMSZ5
CTARn[FMSZ]}.
This field is only valid when DSICR1[DSI64] is enabled.
Interleaved TSB mode.
Enables the Interleaved TSB mode of operation.
When enabled, there is no priority among frames from the SPI/DSI.
DSI frames are sent when either the previous transmission was an SPI frame or the TX_FIFO is
empty.
10
Frames are transmitted on every trigger whose source is selected by the TRG bit setting.
ITSB
ITSB mode requires DSICR0[TSBC] set and should be written only when MCR[HALT] is
asserted. If ITSB bit is set without setting DSICR0[TSBC], DSPI operates in Normal Mode
depending on MCR[DCONF] bit.
See Section 46.5.10: Interleaved TSB (ITSB) Mode
0 Disabled.
1 Enabled.
Timed Serial Bus Configuration.
Enables the Timed Serial Bus Configuration, which allows up to 64-bit data to be used.
11
It also allows t
TSBC
0 Disabled.
1 Enabled.
Transmit Data Source Select.
Selects the source of data to be serialized.
The source can be either: a) data from host software written to the DSPI DSI Alternate
12
Serialization Data Register (ASDR1/0), or b) parallel input pin states latched into the DSPI DSI
TXSS
Serialization Data Register (SDR1/0).
0 SDR source.
1 ASDR source.
Change In Data Transfer Enable
When the CID bit is set, DSI frames are initiated when the current DSI data differs from the
15 previous DSI data shifted out.
CID Do not enable CID when DCONT is enabled.
0 Disabled.
1 Enabled.
DSI Continuous Peripheral Chip Select Enable (DSI Master mode only)
Enables the PCS signals to remain asserted between transfers.
16
When the TSBC bit is set, DCONT has no effect.
DCONT
Do not enable DCONT when CID is enabled.
0 PCS signals return to inactive.
1 PCS signals remain asserted.

Table 624. DSPI_DSICR0 field descriptions

to be programmable.
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