STMicroelectronics SPC572L series Reference Manual page 677

RM0400
Field
Enable Memory 4 Non-Correctable Interrupt Notification
This field is initialized by hardware reset.
17
0 Interrupt notification of Memory 4 non-correctable error events is disabled.
ENCIE4
1 Interrupt notification of Memory 4 non-correctable error events is enabled.
Refer to the device configuration chapter for details on Memory 4 mapping.
Enable Memory 5 Single Correction Interrupt Notification
This field is initialized by hardware reset.
20
0 Interrupt notification of Memory 5 single-bit correction events is disabled.
ESCIE5
1 Interrupt notification of Memory 5 single-bit correction events is enabled.
Refer to the device configuration chapter for details on Memory 5 mapping.
Enable Memory 5 Non-Correctable Interrupt Notification
This field is initialized by hardware reset.
21
0 Interrupt notification of Memory 5 non-correctable error events is disabled.
ENCIE5
1 Interrupt notification of Memory 5 non-correctable error events is enabled.
Refer to the device configuration chapter for details on Memory 5 mapping.
Enable Memory 6 Single Correction Interrupt Notification
This field is initialized by hardware reset.
24
0 Interrupt notification of Memory 6 single-bit correction events is disabled.
ESCIE6
1 Interrupt notification of Memory 6 single-bit correction events is enabled.
Refer to the device configuration chapter for details on Memory 6 mapping.
Enable Memory 6 Non-Correctable Interrupt Notification
This field is initialized by hardware reset.
25
0 Interrupt notification of Memory 6 non-correctable error events is disabled.
ENCIE6
1 Interrupt notification of Memory 6 non-correctable error events is enabled.
Refer to the device configuration chapter for details on Memory 6 mapping.
Enable Memory 7 Single Correction Interrupt Notification
This field is initialized by hardware reset.
28
0 Interrupt notification of Memory 7 single-bit correction events is disabled.
ESCIE7
1 Interrupt notification of Memory 7 single-bit correction events is enabled.
Refer to the device configuration chapter for details on Memory 7 mapping.
Enable Memory 7 Non-Correctable Interrupt Notification
This field is initialized by hardware reset.
29
0 Interrupt notification of Memory 7 non-correctable error events is disabled.
ENCIE7
1 Interrupt notification of Memory 7 non-correctable error events is enabled.
Refer to the device configuration chapter for details on Memory 7 mapping.
32.2.2.2 ERM Status Register (ERM_SR)
This ERM Status Register is a 32-bit control register for signaling which types of ECC
events have been detected for memory channels 0 through 7. The ERM_SR signals the last
memory event to be detected for each memory channel.
Table 329. ERM_CR field descriptions(Continued)
DocID027809 Rev 4
Error Reporting Module (ERM)
Description
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