Table 106. System Call Interrupt—Register Settings - STMicroelectronics SPC572L series Reference Manual

RM0400
12.6.5.8 System Call Interrupt (offset 0x80)
A System Call interrupt occurs when a System Call (se_sc) instruction is executed and no
higher priority exception exists.
Table 106
Register
SRR0 Set to the effective address of the instruction following the system call instruction.
SRR1 Set to the contents of the MSR at the time of the interrupt
SPV 0
WE 0
MSR CE —
EE 0
PR 0
ESR VLEMI. All other bits cleared.
MCSR Unchanged
DEAR Unchanged
Vector IVPR || 0x80
0:23
12.6.5.9 Debug Interrupt (offset 0x90)
There are multiple sources that can signal a Debug exception. A Debug interrupt occurs
when no higher priority exception exists, a Debug exception exists in the Debug Status
Register, and Debug interrupts are enabled (both DBCR0
MSR
=
DE
Table 107
Register
Set to the effective address of the excepting instruction for IAC, BRT, RET, CRET, and TRAP.
Set to the effective address of the next instruction to be executed following the excepting instruction for
(1)
DSRR0 DAC (usually) and ICMP.
For a UDE, IRPT, CIRPT, DCNT, or DEVT type exception, set to the effective address of the instruction
that the processor would have attempted to execute next if no exception conditions were present.
DSRR1 Set to the contents of the MSR at the time of the interrupt
SPV 0
WE 0
MSR CE —/0
EE —/0
PR 0
lists register settings when a System Call interrupt is taken.
Table 106. System Call Interrupt—register settings
FP
ME
FE0
DE
1).
lists register settings when a Debug interrupt is taken.
Table 107. Debug Interrupt—register settings
(2)
2
DocID027809 Rev 4
Setting description
0
—
0
—
Setting description
FP 0
ME —
FE0 0
DE 0
Core e200z215An3 description
FE1 0
IS 0
DS 0
PMM 0
RI —
1 (internal debug mode) and
=
IDM
FE1 0
IS 0
DS 0
PMM 0
RI —
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