Table 1031. Snfa0 Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Sequence Processing Unit (SPU)
63.5.1.6.3 State n false action 0 (SnFA0)
The SPU can be programmed to enable up to four different actions against a false condition
of every state. All the possible actions and their encoding are listed in
12 bits are needed to code every action. The first two actions for a false condition are
defined in SnFA0 and the next two actions are defined in SnFA1.
format of the SnFA0 register where the state number, n = 0–7.
0x11 (State0)
0x13 (State1)
0x15 (State2)
0x17 (State3)
Offset
0x19 (State4)
0x1B (State5)
0x1D (State6)
0x1F (State7)
31 30 29 28 27
R 0 0 0 0
W
Reset 0 0 0 0 0
The SnFA0 register fields are described in
Field
0–11
Action 1 to be performed for State n false condition. The decoding of these bits is defined in
Table 1028
ACTION1
12–15 Reserved
16–27
Action 2 to be performed for State n false condition. The decoding of these bits is defined in
Table 1028
ACTION2
28–31 Reserved
63.5.1.6.4 State n false action 1 (SnFA1)
The SPU can be programmed to enable up to four different actions against a false condition
of every state. All the possible actions and their encoding are listed in
12 bits are needed to code every action. The first two actions for false condition are defined
in SnFA0 and the next two actions are defined in SnFA1.
the SnFA1 register where the state number, n = 0–7.
1848/2058
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
ACTION2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 1088. SnFA0 register format

Table 1031. SnFA0 register field descriptions

DocID027809 Rev 4
0 0 0 0
Table 1031.
Description
Figure 1089
RM0400
Table 1028. A total of
Figure 1088 shows the
Access: User read/write
8 7 6 5 4 3 2
ACTION1
Table 1028. A total of
shows the format of
1 0