Table 1024. Sctrl Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Sequence Processing Unit (SPU)
Field
Output AND Gate 3 Control.
6
0 Output is used directly (without inversion) for this event
OutAND3
1 Output is inverted for this event
Output of AND Gate 4 Control.
7
0 Output is used directly (without inversion) for this event
OutAND4
1 Output is inverted for this event
Output OR GATE Control.
8
0 Output is used directly (without inversion) for this event
OutOR
1 Output is inverted for this event
9–31 Reserved. Read returns 0.
63.5.1.3.2 Sequence control (SCTRL)
This configuration register is provided to enable the sequence and to select the states that
are part of a particular sequence. There can be at most four active sequences. Each
sequence can have one state or a maximum of eight states. However, each state can only
be used in one unique sequence. In other words, if one state has been selected for a
sequence, then this state cannot be used for any other defined sequence. Each sequence
has a start state and end state.
Offset 0x3F
31 30 29
R 0
ST2
W
Reset 0 0 0
15 14 13
R 0
ST2
W
Reset 0 0 0
The SCTRL register fields are described in
Field
Sequence1 Enable/Disable. Once enabled, this bit is disabled at the end of the Sequence 1.
0
0 Sequence 1 is disabled
ST0
1 Sequence 1 is enabled
3–1 Sequence 1 Start State.
ST1 000 State 0 (Always)
1838/2058
Table 1023. IOICn register field descriptions(Continued)
28 27 26
ST1
0 0 0
12 11 10
ST1
0 0 0
Figure 1082. SCTRL register format

Table 1024. SCTRL register field descriptions

DocID027809 Rev 4
Description
Figure 1082 shows the format of the SCTRL register.
25 24 23 22
0
ST0
0 0 0 0
9 8 7 6
0
ST0
0 0 0 0
Table 1024.
Description
Access: User read/write
21 20 19 18
ST2 ST1
0 0 0 0
5 4 3 2
ST2 ST1
0 0 0 0
RM0400
17 16
ST0
0 0
1 0
ST0
0 0