Functional Description - STMicroelectronics SPC572L series Reference Manual

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28.5

Functional description

As shown in
bus port, Nexus trace, flash memory array, overlay RAM, system RAM, and off-chip Buddy
Device.
For accesses targeting the flash array, the flash memory controller generates read and write
enables, array address, write size and write data as inputs to the flash array. The flash
memory controller captures read data from the flash array and drives it onto the AHB
system bus. Up to four pages of data (128-bit page size) may be buffered in each of two
ways of the flash memory controller mini-cache. Lines may be prefetched in advance of
being requested, allowing single-cycle (zero AHB wait-states) read data responses on buffer
hits.
Several prefetch control algorithms are available for controlling line read buffer fills. Prefetch
triggering may be restricted to instruction accesses only, data accesses only, or may be
unrestricted. Prefetch triggering may also be controlled on a per-master basis.
Buffers may also be selectively enabled or disabled for allocation by instruction and data
prefetch.
Access protections may be applied on a per-master basis for both reads and writes to
support security and privilege mechanisms.
28.5.1 Basic interface protocol
Read accesses are terminated under control of the appropriate wait state settings. Thus, the
access time of the operation is determined by the setting of the PFCR1[RWSC] field.
Access timing can be varied to account for the operating conditions of the SoC (frequency,
voltage, temp) by appropriately setting the PFCR1[RWSC] field.
28.5.2 Access protections
28.5.2.1 PFAPR - Platform Flash Access Protection Register (PFAPR)
The flash memory controller provides programmable, configurable access protections for
both read and write cycles on a per-master basis via the PFlash Access Protection Register
(PFAPR). It allows restriction of read and write requests on a per-master basis. This
functionality is described in
(PFAPR). Detection of a protection violation results in an error response from the flash
memory controller on the AHB transfer.
28.5.2.2 BAF execution disable
The flash memory controller provides a mechanism to disable instruction execution of the
BAF (Boot Assist Flash) code, which is loaded in a predetermined OTP flash block. Setting
the BAF Disable field (BAF_DIS) in the PFlash Configuration Register 3 (PFCR3) prevents
execution of the BAF instructions. When this field is set, all incoming requests from the
system bus on either Port0 or Port1 are evaluated. If the flash memory controller detects an
attempted instruction fetch access to the BAF region of the flash, the flash memory
controller aborts the access and returns a system bus error. Data accesses to the BAF
region are not affected by the state of PFCR3[BAF_DIS].
Figure 237 the flash memory controller interfaces between the AHB system
Section 28.4.1.3: Platform Flash Access Protection Register
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Flash memory controller (PFLASH Controller)
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