Protocols - STMicroelectronics SPC572L series Reference Manual

RM0400
The CJTAG module supports T4 functionality that includes STL, RSU, EPU, and APU
hardware layers.
2 pin (TCKC, TMSC)
4 pin (TCKC, TMSC, TDIC, TDOC)
4 pin (TCK, TMS, TDI(C), TDO(C))
4 pin (TCK, TMS, TDI(C), TDO(C))
4 pin (TCK, TMS, TDI, TDO)
60.3.5

Protocols

The TAP.7 architecture utilizes the three protocols shown in
The Standard Protocol transfers data with the TMS(C) signal value being sampled with a
TCK(C) edge. The Advanced and Control Protocols use both data transferred with the
TMS(C) signal value being sampled with a TCK(C) signal edge and escape sequences.
The Standard Protocol may be used to switch to the use of the Advanced Protocol and vice
versa. The Control Protocol can also be used to switch between the use of the Standard
and the Advanced Protocol. The mandatory and optional deployment of these protocols
with the TAP.7 classes is shown in
IEEE 1149.7 Compact JTAG Test Access Port Controller (CJTAG)
Figure 1026. TAP.7 Controller Architecture
RSU
RSU
RSU
(optional)
RSU
(optional)
Figure 1027. TAP.7 Behaviors
Standard
Scan transfers
(4-pin)
DocID027809 Rev 4
Advanced Behavior
APU EPU
EPU
EPU
TAP.7 Controller
Control
(2-pin)
Advanced
(2-pin)
Table 973.
Extended Behavior
Compliant
STL
STL
STL
STL
System
Test
Logic
Figure 1027.
Reset Online/Offline
Scan transfers
Non-scan transfers
T4
T3
T1, T2
T0
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