Table 619. Dspi_Pushr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Deserial Serial Peripheral Interface (DSPI)
Address: Base + 0x0034
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 590. DSPI PUSH FIFO Register In Master Mode (DSPI_PUSHR)
Field
Continuous Peripheral Chip Select Enable. (SPI master mode)
Continuous Selection Format enables the selected PCS signals to remain asserted between
transfers.
0
PUSHR[EOQ] and PUSHR[CONT] bits cannot be asserted together in any Command Frame as
CONT EOQ signifies the last frame in a queue and the Last frame in a Continuous Transfer must have
PUSHR[CONT] as 0.
0 Return PCSn signals to their inactive state between transfers.
1 Keep PCSn signals asserted between transfers.
Clock and Transfer Attributes Select.
Selects which CTAR (and corresponding CTARE register) to use in master mode to specify the
transfer attributes for the associated SPI frame.
In SPI slave mode, CTAR0 is used.
See the Device Configuration chapter to determine how many CTARs this device has. Do not
program a value in this field for a register that is not present.
1–3
000 CTAR0/CTARE0
CTAS
001 CTAR1/CTARE1
010 CTAR2/CTARE2
011 CTAR3/CTARE3
100 CTAR4/CTARE4
101 CTAR5/CTARE5
110 CTAR6/CTARE6
111 CTAR7/CTARE7
End Of Queue
Host software uses this bit to signal to the DSPI that the current SPI transfer is the last in a
4
queue. DSPI_SR[EOQF] is set at the end of the transfer.
EOQ
0 The SPI data is not the last data to transfer.
1 The SPI data is the last data to transfer.
1160/2058
2 3 4 5
CTAS EOQ
0 0 0 0
18 19 20 21
0 0 0 0

Table 619. DSPI_PUSHR field descriptions

6 7 8
0 0 0
22 23 24
TXDATA
0 0 0
Description
DocID027809 Rev 4
Access: User read/write
9 10 11 12
PCS[7:0]
0 0 0 0
25 26 27 28
0 0 0 0
RM0400
13 14 15
0 0 0
29 30 31
0 0 0