Table 791. Chnl_En Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Address Offset: 0x0004
0
R
W
Reset 0
8
R
W
Reset 0
16
R
EN_CH15
W
Reset 0
24
R
EN_CH7
W
Reset 0
Field
0:15 Reserved. Read returns zero
Enable bits for Channels 0 to 15. All channels are disabled after reset. User software must program
all channel parameters before setting this bit. Once set, other channel parameters in registers
should not be changed until this bit is cleared. Only Interrupt Enable and Status bits can be written
16:31
to.
EN_CHn
(n = 15 to 0)
0 – Channel is disabled
1 – Channel is enabled. Channel parameter registers are locked for writing
49.3.2.3 Global Status Register (GBL_STATUS)
This register provides the status of various conditions in the module that are common
across all channels.
1 2
0 0
9 10
0 0
17 18
EN_CH14 EN_CH13
0 0
25 26
EN_CH6 EN_CH5
0 0
Figure 779. Channel Enable Register (CHNL_EN)

Table 791. CHNL_EN field descriptions

DocID027809 Rev 4
3 4
0 0
11 12
0 0
19 20
EN_CH12 EN_CH11
0 0
27 28
EN_CH4 EN_CH3
0 0
Description
SENT Receiver (SRX)
5 6
0 0
13 14
0 0
21 22
EN_CH10 EN_CH9
0 0
29 30
EN_CH2 EN_CH1
0 0
Access: RW
7
0
15
0
23
EN_CH8
0
31
EN_CH0
0
1369/2058
1410