Register Descriptions - STMicroelectronics SPC572L series Reference Manual

GTM101 Integration (GTMINT) Module
2. For detailed information see the GTM-IP Specification document.
3. Reset value depends on configuration parameters.
4. RAM reserved position for GTM-IP internal use. No error occurs when accessed.
43.2.2

Register descriptions

This section contains the description of additional registers on the top integration module.
Description of GTM-IP registers, or GTMDI registers are found in their respective
specification document.
43.2.2.1 GTM Module Configuration Register (GTMMCR)
The GTMMCR contains the control bits to configure the general operation of the GTMINT
and GTM-IP Module.
.
Offset 0x000C0
0 1
R 0
W
(1)
Reset 0 —
16 17 18
R 0
W
—
<Cros
s
Reset 0
Refs>
1
Figure 467. GTM Module Configuration Register (GTMMCR)
1. Reset value is SoC dependent.
GTMMCR register functions are as shown in
Field
MDIS Module Disable. The MDIS bit puts the GTMINT Module in stop/disabled mode.
Communication through the slave-bus Interface is ignored in this mode except reads/writes to
1
the GTMMCR and reads from other integration registers which are allowed.
MDIS
1 Module disable request
0 Normal Mode
984/2058
2 3 4 5
0 0 0 0
0 0 0 0
19 20 21
0 0 0 0
0 0 0 0
Table 517. GTMMCR field descriptions
DocID027809 Rev 4
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Table 517.
Description
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
0 0 0 0
RM0400
14 15
0
0 0
30 31
0 0
0 0