Figure 40. Vdd_Hv Monitored Voltages During Power-Up - STMicroelectronics SPC572L series Reference Manual

Power management
LVD290_IF
1. After both LV and HV POWERUP exit conditions have been verified, ipp_por_en_b
signal is released to all analog modules.
2. The IRCOSC module starts initialization and provides the clock to the system after
t
RCSTARTUP
LVD400_IM is masked. All other HV LVDs remain active.
LVD270_C and LVD400_IM share the same reference. The LVD400_IM - LVD270_C
difference represents the margin with respect to the maximum internal resistive drop
and hysteresis addressing external supply drop.
3. The device proceeds through the RGM reset sequence: PHASE0–PHASE1–PHASE2–
PHASE3.
4. Voltage detector (LVD) modules are trimmed at the beginning of PHASE3.
–
–
–
–
5. The configurable LVD modules can optionally be unmasked at the end of PHASE3.
Mask information is read as DCF record from the flash UTEST option bits.
Figure 44
sequence from POWERUP to PHASE3.
Internal LVD270_C is enabled during PHASE3.
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Figure 40. VDD_HV monitored voltages during power-up

VDD_HV_IF
pin
DEVICE
LVD400_A
. PMC digital interface reset is released after two RC clock cycles and
Trim values for LVDs are stored as internal DCF records.
The SSCM uses the flash low-voltage (low-speed) read feature to access the DCF
records and apply the trim values to each LVD module.
After analog delay (t
LVDTRIM
have been trimmed and supply is above threshold
the SSCM proceeds with the reset sequence, eventually accessesing the flash at
full speed to read the option bits required to complete device configuration.
provides the threshold variation of VDD_HV LVDs monitor during power-up
DocID027809 Rev 4
VDD_HV_FLA
pin
VDD_HV_PMC pin
VDD_HV_ADC
) has elapsed, the PMC acknowledges that all LVDs
LVD270_C
LVD290_F
VDD_HV_IM pin
LVD400_IM
VDD_HV_IJ pin
LVD290_IJ
RM0400