Priority Management - STMicroelectronics SPC572L series Reference Manual

Interrupt Controller (INTC)
Any Processor n will be allowed to write to any of the SET bits in the Software Set/Clear
Interrupt registers. The CLR bit will only be writable by the Processor n which has been
assigned to handle that interrupt request, as determined by the setting of the
INTC_PSRn[PRC_SELn] bits.
18.6.1.3 Unique vector for each interrupt request source
Each peripheral and software-settable interrupt request is assigned a hardwired unique 10-
bit vector. Software-settable interrupts 0–31 are assigned vectors 0–31, respectively. The
peripheral interrupt requests are assigned vectors from 32 to a number as high as needed
to cover all peripheral interrupt requests.
18.6.2

Priority management

The asserted interrupt requests are compared to each other based on their PRIn and
PRC_SELn values set in INTC_PSRn. The result of that comparison also is compared to
PRI in the associated INTC_CPRn. The results of those comparisons are used to manage
the priority of the ISR being executed by the associated processor. The associated LIFO
also assists in managing that priority.
18.6.2.1 Current priority and preemption
The priority arbitrator, selector, encoder, and comparator logic shown in
to compare the priority of the asserted interrupt requests to the current priority. If the priority
of any asserted peripheral or software-settable interrupt request is higher than the current
priority for a given processor, then the interrupt request to the processor is asserted. Also, a
unique vector for the preempting peripheral or software-settable interrupt request is
generated for the associated INTC_IACKRn, and if in hardware vector mode, for the
interrupt vector provided to the processor.
18.6.2.1.1 Priority tree
The priority tree for each processor compares all the priorities of all of the asserted interrupt
requests assigned to that processor, both peripheral and software-settable. The output of
the priority tree is the highest of those priorities assigned to a given processor. Also, any
interrupt requests which have this highest priority are output as asserted interrupt requests
to the associated selector logic.
18.6.2.1.2 Selector
If only one interrupt request from the associated priority tree is asserted, then it is passed as
asserted to the associated encoder logic. If multiple interrupt requests from the associated
priority tree are asserted, then only the one with the lowest vector is passed as asserted to
the associated encoder logic. The lower vector is chosen regardless of the time order of the
assertions of the peripheral or software-settable interrupt requests.
18.6.2.1.3 Encoder
The encoder logic generates the unique 10-bit vector for the asserted interrupt request from
the request selector subblock for the associated processor.
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Figure 106 are used