Figure 838. Slave Node — Dma Rx Fsm (Concept Scheme) - STMicroelectronics SPC572L series Reference Manual

LINFlexD
50.3.5.7 UART — TX mode
In UART TX mode, the DMA interface requires a DMA TX channel. A single TCD can
control the transmission of an entire Tx buffer. The memory map associated with the TCD
chain (RAM area and LINFlexD registers) is given in
TCD(n)
TCD(n +1)
1450/2058
Figure 838. Slave node — DMA Rx FSM (concept scheme)
Enables DMA Rx channel/filter request
(DMAERQH, DMAERQL)
!DTF & (DRF & | (DBFF & RMB))
& (IFMI! = 0) & DMA_REN?
True
DMA Rx transfer (Req/Ack minor/major loop) from
LINFlexD regs to RAM area (channel/filter mapping)
DMA Rx transfer done?
True
True
Clear DRF
Figure 839. UART — TX memory map
RAM area
DMA transfer (8/16 data format)
BDRL (M bytes)
BDRL + DRM
(8 bytes)
BDRL (M halfwords)
BDRL (M bytes)
BDRL + DRM
(8 bytes)
BDRL (M halfwords)
1 DMA TX channel/filter (TCD single and/or linked chain)
DocID027809 Rev 4
False
DRF?
Figure
LINFlexD regs
(4 bytes FIFO mode)
BDRL + DRM
BDRL
(8 bytes)
(2 halfwords FIFO mode)
(4 bytes FIFO mode)
BDRL + DRM
BDRL
(8 bytes)
(2 halfwords FIFO mode)
False
False
False
DBFF & RMB?
True (extended frame
Clear DBFF.RMB
(for extended frame)
839.
BDRL
BDRL
Buffer (n+1)
RM0400
size > 8 bytes)
Buffer (n)