System Timer Module (Stm) - STMicroelectronics SPC572L series Reference Manual

System Timer Module (STM)

39 System Timer Module (STM)
39.1 Introduction
39.1.1 Overview
The System Timer Module (STM) is a 32-bit timer designed to support commonly required
system and application software timing functions. The STM includes a 32-bit up counter and
four 32-bit compare channels with a separate interrupt source for each channel. The counter
is driven by the system clock divided by an 8-bit prescale value (1 to 256).
39.1.2 Features
The STM has the following features:
•
One 32-bit up counter with 8-bit prescaler
•
Four 32-bit compare channels
•
Independent interrupt source for each channel
•
Counter can be stopped in debug mode
39.1.3 Modes of operation
The STM supports two device modes of operation: normal and debug. When the STM is
enabled in normal mode, its counter runs continuously. In debug mode, operation of the
counter is controlled by the FRZ bit in the STM_CR register. If the FRZ bit is set, the counter
is stopped in debug mode, otherwise it continues to run.
39.2 External signal description
The STM does not have any external interface signals.
39.3 Memory map and register definition
The STM programming model has fourteen 32-bit registers. The STM registers can only be
accessed using 32-bit (word) accesses. Attempted references using a different size or to a
reserved address generates a bus error termination.
39.3.1 Memory map
The STM memory map is shown in
Address offset
0x0000
0x0004
0x0008
0x000C
846/2058
Table
Table 434. STM memory map
STM Control Register (STM_CR)
STM Counter Value (STM_CNT)
Reserved
Reserved
DocID027809 Rev 4
434.
Register
RM0400
Location
on page 847
on page 848