Table 1017. C2Pevp Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Offset 0x0C
31 30
R
Mux63
W
Reset 0 0
15 14
R
Mux55
W
Reset 0 0
63.5.1.1.11 CPU2 processor exception vector prefix (C2PEVP)
The SPU captures the exception vector from CPU2 when the exception enable signal is
asserted. The exception vector decoding is defined in
captured vector with the value in the C2PEVP register.
the C2PEVP register.
Offset 0x0F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The C2PEVP register is described in
Field
CPU2 processor exception vector. Program this field with one of the vector values from
15–0 select the corresponding processor exception.
CPU2 Note: This field must use the byte swapped values in the CnPEVP register CPUn field value column in
Table 1040.
31–16 Reserved
63.5.1.1.12 CPU2 interrupt priority selection (C2PIS)
Figure 1075
vector from CPU2 with the value programmed to the C2PIS register and generates a
match signal if necessary. The typical use case would be for posedge detection on match
(to detect when the priority level is set to the compare value) or high detection while match
remains.
29 28 27 26
Mux62 Mux61
0 0 0 0
13 12 11 10
Mux54 Mux53
0 0 0 0
Figure 1073. ITLD3 register format
Figure 1074. C2PEVP register format

Table 1017. C2PEVP register field descriptions

shows the format of the C2PIS register. The SPU compares the input CPR
DocID027809 Rev 4
25 24 23 22
Mux 60 Mux59
0 0 0 0
9 8 7 6
Mux52 Mux51
0 0 0 0
Table
Table 1017.
Description
Sequence Processing Unit (SPU)
Access: User read/write
21 20 19 18
Mux58 Mux57
0 0 0 0
5 4 3 2
Mux50 Mux49
0 0 0 0
1040. The SPU compares this
Figure 1074 shows the format of
Access: User read/write
8 7 6 5
CPU2
Table 1040
17 16
Mux56
0 0
1 0
Mux48
0 0
4 3 2 1 0
to
1829/2058
1863