Table 937. Mc_Me System Clock Selection Overview - STMicroelectronics SPC572L series Reference Manual

Mode Entry Module (MC_ME)
If the value of the PWRLVL field of the ME_<target mode>_MC register not equal to that of
the ME_<current mode>_MC register's, a progresive clock switching is performed.
The current system clock configuration can be observed by reading the S_SYSCLK bit field
of the ME_GS register, which is updated after every system clock switching. Until the target
clock is available, the system uses the previous clock configuration.
System clock switching starts only after
•
the
is one of the following:
–
–
–
•
the
system clock frequency before peripherals close their internal activitiesthe
Clocks Enable
An overview of system clock source selection possibilities for each mode is shown in
Table 937. A '
System clock
source
RESET
16 MHz
√
internal RC
(default)
oscillator
external
crystal
oscillator
PLL0 PHI
system clock
is disabled
1. disabling the system clock during
56.4.3.14 Pad Switch-Off
If the PDO bit of the ME_<target mode>_MC register is '1' then
• the outputs of the pads are forced to the high impedance state if the target mode is
SAFE
This step is executed only after the
56.4.3.15 Clock Sources Switch-Off
Based on the chip mode and the <clock source>ON bits of the ME_<mode>_MC registers,
if a given clock source is to be switched off, the MC_ME requests the clock source to power
1638/2058
Clock Sources Switch-On
the 16 MHz internal RC oscillator
the external crystal oscillator
the primary PLL
Peripheral Clocks Disable
processe has completed
' indicates that a given clock source is selectable for a given mode.
√

Table 937. MC_ME System Clock Selection Overview

TEST
√
(default)
√
√
(1)
√
TEST mode will require a reset in order to exit
or TEST
process has completed if the target system clock source
process has completed in order not to change the
Mode
SAFE DRUN
√ √
(default) (default)
√
√
Peripheral Clocks Disable
DocID027809 Rev 4
RUN0...3 HALT0
√ √
(default) (default)
√ √
√ √
TEST mode
process has completed.
RM0400
Peripheral
STOP0
√
(default)
√