External Signal Description - STMicroelectronics SPC572L series Reference Manual

Debug and Calibration Interface (DCI)
MCKO
(internal)
EVTO_in
(internal)
EVTO Pad
Output (Tool)
Output immediately
asserted
58.1.3.8 Reset control
The DCI includes control bits to allow a connected tool to force a reset of the connected
device. The description is as follows:
•
Force functional reset—This reset is generated by programming the
DCI_CR[FPD_FUNC] bit. When set, it forces functional reset. This bit has to be reset
by the tool to negate the reset signal.
•
Force POR or destructive reset—This reset is generated by programming
DCI_CR[FPD_DEST] bit. When set it forces destructive reset. This bit has to be reset
by the tool to negate the reset signal.
These reset signals are directly connected to the respective DCI_CR bits. The DCI does not
reset the DCI_CR bits after generation of the respective reset signals. The tool must
specifically reset the appropriate DCI_CR bits to remove the reset signals. These reset
control bits can be set/reset through JTAG programming, and only reset through JCOMP
assertion or Power-on-reset.
58.2

External signal description

The JTAGC module used inside DCI module defines the interface with external signals. It
consists of five signals (TMS/TDI/TDO/TCK/JCOMP) that connect to off chip development
tools and allow access to test support functions. For more details for JTAG signals, refer to
JTAGC documentation.
58.3 Register description
The PD DCI module contains two registers, DCI_CR and DCI_PINCR, which are present
inside the JTAGC module. These registers are only controlled using the JTAGC TAP and no
memory-mapped registers are present.
58.3.1 DCI control register (DCI_CR)
The DCI_CR is a 32-bit data register. This register is programmed using JTAG shift with the
corresponding enable instruction described in the JTAGC chapter.
format of the DCI_CR.
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Figure 1018. DCI EVTO timing diagram
EVTO stretched for 1 MCKO
DocID027809 Rev 4
RM0400
Figure 1019 shows the