Interrupt/Dma Request Support - STMicroelectronics SPC572L series Reference Manual

Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface
In case of a hardware trigger, the skew/jitter will be less than 100 ns. It will be more than one
ADC clock cycle due to synchronization. In case of a software trigger, all SDADCs start
synchronous sampling.
Wraparound Control Mechanism: In wraparound control mode, hardware and software
triggers are equally valid. The hardware trigger source should be selected before enabling
the wraparound mode.
35.7.10

Interrupt/DMA request support

The SDADC has one condition that generates interrupts only and another that generates
interrupts or DMA request.
The DFFF field is asserted when the data FIFO full condition is detected, indicating that the
number of converted datawords stored in data FIFO is equal to or greater than the value
indicated by threshold determined by FCR[FTHLD]. The interrupt or DMA request is
generated only when RSER[DFFDIRE] is asserted. RSER[DFFDIRS] selects whether a
DMA request or an interrupt request is generated.
The data FIFO overrun flag (DFORF) indicates the FIFO overflow condition. Further
converted datawords cannot be received and data is lost. The interrupt request is generated
only when RSER[DFORIE] is asserted.
If RSER[GDIGE] is set, all module interrupt/DMA requests are qualified only when an
external global gating signal is asserted.
35.7.11 Gain calibration support
To perform gain calibration, the following sequence needs to be applied.
1. Select differential mode of operation by writing MCR[MODE] to '0'.
2. Enable gain error calibration mode by writing MCR[GECEN] to '1'.
3. Configure the mux selection ANCHSEL field of CSR to '110'. This configuration will
apply VREFP on positive terminal and VREFN on negative terminal.
4. Disable the bias on all input analog channels by writing ENBIAS field of CSR to 0x00.
5. Disable the high-pass filter by deasserting MCR[HPFEN].
6. Generate a reset event by writing 0x5AF0 to RESET_KEY of RKR.
7. Read the digital output (CDR[CDATA]) stored in FIFO after the output settling time.
Expected output if there is no gain error is 0b0111_1001_1001_1001, corresponding to
full positive scale after attenuation inserted by the internal filter (1*0.95). The
measurement should be repeated to reduce contribution of noise during calibration
process. D
AVERAGE(CDR[CDATA]).
8. Change the mux selection ANCHSEL field of CSR to '111'. This configuration will apply
VREFN on positive terminal and VREFP on negative terminal.
9. Generate a reset event by writing 0x5AF0 to RESET_KEY of RKR.
10. Read the digital output (CDR[CDATA]) stored in FIFO after the output settling time.
Expected output if there is no gain error is 0b1000_0110_0110_0110, corresponding to
full negative scale after attenuation inserted by the internal filter (-1*0.95). The
measurement should be repeated to reduce contribution of noise during calibration
752/2058
is the average value of attenuated positive full scale given by D
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