Figure 1011.Cpu Scan Chain Register (Cpuscr) - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
57.5.9.1
Instruction Register (IR)
The Instruction Register (IR) provides a mechanism for controlling the debug session by
serving as a means for forcing in selected instructions, and then causing them to be
executed in a controlled manner by the debug control block. The opcode of the next
instruction to be executed when entering debug mode is contained in this register when the
scan-out of this chain begins. This value should be saved for later restoration if continuation
of the normal instruction stream is desired.
On scan-in, in preparation for exiting debug mode, this register is filled with an instruction
opcode selected by debug control software. By selecting appropriate instructions and
controlling the execution of those instructions, the results of execution may be used to
examine or change memory locations and processor registers. The debug control module
external to the processor core will control execution by providing a single-step capability.
Once the debug session is complete and normal processing is to be resumed, this register
may be loaded with the value originally scanned out.
57.5.9.2 Control State Register (CTL)
The Control State Register (CTL) is a 32-bit register that stores the value of certain internal
CPU state variables before the debug mode is entered. This register is affected by the
operations performed during the debug session and should normally be restored by the
1710/2058
Figure 1011. CPU Scan Chain Register (CPUSCR)
32
0
WBBR
32
0
WBBR
32
0
MSR
32
0
PC
32
0
IR
32
0
CTL
DocID027809 Rev 4
31
low
31
high
31
31
31
31
RM0400
TDO
TCK
TDI