Functional Description - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
The Test Mode Disable Check register is used as a location to provide a password challenge to
unlock blocks selected to be sealed as part of the Test Mode Disable seal mechanism. Please
see Section 29.4.6.2, Test mode disable
Writes to the register have no effect except for a password challenge.
0–31
Reads to this register will always return 0.
PWD
The register's reset value is 0.
Note: PWD bitfield is byte-reversed compared to UTEST TMD password : for instance, if UTEST
29.4

Functional description

This chapter describes the details of all the modes of operation available to the Flash
Memory module.
29.4.1 Reset
A reset is the highest priority operation for the Flash Memory module and terminates all
other operations.
The Flash Memory module uses reset to initialize register and status bits to their default
reset values. If the Flash Memory module is executing a Program or Erase operation
(MCR[PGM]=1 or MCR[ERS]=1) and a reset is issued, the operation is immediately
terminated and the module disables the high voltage logic without damage to the high
voltage circuits.Reset terminates all operations and forces the Flash Memory module into
Read mode ready to receive Read/Write accesses.
Reset and Power-Off must not be used as a systematic way to terminate a Program or
Erase operation.
After reset is negated Read register access may be
require updating from shadow information or other inputs may not read updated values until
MCR[DONE]transforms. MCR[DONE] may be polled to determine if the Flash Memory
module has transitioned out of reset. Note that the registers cannot be written until
MCR[DONE] is high.
29.4.2 Power-down mode (Disable mode)
The Power-down (or Disable) modeallows the turning-off of all flash DC current sources. All
power dissipation in this mode is due solely to leakage.
In Power-down mode no Read from or Write to the flash array is possible. Every Flash array
Read access executed when the Power-down mode is active outputs invalid data.
The user may not read some registers (UM0–UM9 and part of UT0) until the Power-down
mode is exited.On the contrary, Write access is locked on all the registers in Power-down
mode.
Table 322. TMD field descriptions
TMD password is written 0x01020304, the PWD bitfield must be written 0x04030201
DocID027809 Rev 4
Embedded Flash Memory (MP55)
Description
for more information.
performed, although registers that
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