Figure 151. Dma Operation, Part 1 - STMicroelectronics SPC572L series Reference Manual

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memory for TCDn. Next, the TCD memory is accessed and the descriptor read from the
local memory and loaded into the eDMA engine address path channel x or y registers. The
TCD memory is 64 bits wide to minimize the time needed to fetch the activated channel
descriptor and load it into the address path channel x or y registers.
Read Data
Write Data
Address
In the second part of the basic data flow as shown in
with the data transfer (address path, data path, and control) sequence through source reads
and destination writes to perform the actual data movement. The source reads are initiated
and the fetched data is temporarily stored in the data path block until it is gated onto the
internal bus during the destination write. This source read/destination write processing
continues until the minor byte count has transferred.
Enhanced Direct Memory Access (eDMA)

Figure 151. DMA operation, part 1

Transfer
Control
Descriptor (TCD)
eDMA Peripheral
Request
DocID027809 Rev 4
Write Address
Write Data
Read Data
eDMA Done
Figure 152 the modules associated
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