Figure 531. Bypass Operation - STMicroelectronics SPC572L series Reference Manual

RM0400
For details of signals refer to
44.3.16.1 Operating Conditions
The Clock Calibration on CAN unit is designed to operate under the following conditions:
•
Clock input from PLL (cu_pclk) between 80 MHz and 500 MHz
•
M_CAN bit rates between 125 kbit/s and 1 Mbit/s
•
Clock for Host accesses (cu_hclk) is 40/50 MHz
The Clock Calibration on CAN unit generates a calibrated time quanta clock cu_tqc in the
range from 0.5 MHz to 25 MHz.
Note: The M_CAN requires that the CAN clock is always below or equal to the Host clock
(m_can_cclk < m_can_hclk). This has to be considered when the Clock Calibration on CAN
unit is bypassed (CCFG.BCC = '1').
44.3.16.2 Calibration Accuracy
The calibration accuracy in state Precision_Calibrated depends on:
•
The dynamic clock tolerance at the clock input cu_pclk
•
The measurement error. For each bit sequence used for calibration measurement,
there is a maximum error of one cu_pclk period. The number of bits used for
measurement of the bit time is 32 or 64-bit, depending on configuration of CCFG.CFL.
•
Tolerable error in calibration mechanism
The distance between two calibration messages has to be chosen to fit the clock tolerance
requirements of the attached M_CANs.
Note: Dynamic clock tolerance is the clock frequency variation between two calibration messages
e.g. caused by change of temperature or operating voltage.

Figure 531. Bypass operation

Table 585: Calibration on CAN Module Interface
DocID027809 Rev 4
CAN Subsystem
1075/2058
1091