Table 400. Tcimr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter-
36.5.1.22 Test Channel Interrupt Mask Register (TCIMR)
The interrupt mask register to channel association is described in
Offset 0x404
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 350. Test Channel Interrupt Mask Register (TCIMR)
Field
0–31
IM_CH[x]
Table 401. Test Channel Interrupt Mask Register to Channel Association
Parameter num_testch vector has positional inference for TCIMR such that num_testch(i)
(i = 0–31) corresponds to TCIMR bit[0:31]. If any of the num_testch(i) value is '0', the
corresponding bit is not implemented and read access returns '0' on that bit location.
If the complete num_testch is all 0's, TCIMR is not implemented and treated as reserved
space. Any attempt to access this space generates a transfer error.
36.5.1.23 Test Channel DMA Select Register (TCDSR)
The DMA select registers to channel association is described in
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0

Table 400. TCIMR field descriptions

IM_CH[x]: Interrupt mask bit for channel x
0 Interrupt for CH[x] is disabled.
1 Interrupt for CH[x] is enabled.
Register
TCIMR
DocID027809 Rev 4
6 7 8 9
IM_CH[x]
0 0 0 0
22 23 24 25
IM_CH[x]
0 0 0 0
Description
Table 401.
Access: User Read/Write
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
Register bits 31:0
IM_CH[127:96]
Table 403.
14 15
0 0
30 31
0 0
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