Table 100. Machine Check Interrupt—Register Settings - STMicroelectronics SPC572L series Reference Manual

RM0400
1. Clearing of DE is optionally supported by control in HID0.
The MSR
configured to be cleared via the HID0 register (HID0
12.6.5.2 Machine Check Interrupt (offset 0x10)
The EIS Machine Check APU defines a separate set of save/restore registers (MCSRR0/1),
a Machine Check Syndrome Register (MCSR) to record the source(s) of machine checks,
and a Machine Check Address Register (MCAR) to hold an address associated with a
machine check for certain classes of machine checks. Return from Machine Check
instructions (se_rfmci) are also provided to support returns using MCSRR0/1.
The MSR
configured to be cleared or left unchanged via the HID0 register (HID0
When a Machine Check interrupt is taken, registers are updated as shown in
Register
On a best-effort basis, set to the address of some instruction that was executing or about to be
MCSRR0
executing when the machine check condition occurred.
MCSRR1 Set to the contents of the MSR at the time of the interrupt
SPV 0
WE 0
MSR CE 0
EE 0
PR 0
ESR Unchanged
Updated to reflect the source(s) of a machine check. Hardware only sets appropriate bits, no previously
MCSR
set bits are cleared by hardware.
Vector IVPR || 0x10
0:23
1. Clearing of DE is optionally supported by control in HID0.
12.6.5.3 Data Storage Interrupt (offset 0x20)
A Data Storage interrupt (DSI) may occur if no higher priority exception exists and a Read or
Write Access Control exception condition exists.
Table 101
Register
SRR0 Set to the effective address of the excepting load/store instruction.
SRR1 Set to the contents of the MSR at the time of the interrupt
bit is not automatically cleared by a Critical Input interrupt, but it can be
DE
bit is not automatically cleared by a Machine Check exception, but it can be
DE
Table 100. Machine Check Interrupt—register settings
FP
ME
FE0
DE
lists register settings when a DSI is taken.
Table 101. Data Storage Interrupt—register settings
DocID027809 Rev 4
CICLRDE
Setting description
0
0
0
(1)
0/—
Setting description
Core e200z215An3 description
).
).
MCCLRDE
Table
FE1 0
IS 0
DS 0
PMM 0
RI 0
100.
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