Figure 620. Dspi Transfer Timing Diagram (Mtfe = 0, Cpha = 1, Fmsz = 8) - STMicroelectronics SPC572L series Reference Manual

RM0400

Figure 620. DSPI transfer timing diagram (MTFE = 0, CPHA = 1, FMSZ = 8)

(CPOL = 0)
SCK
(CPOL = 1)
SCK
Master and Slave
Sample
Master SOUT/
Slave SIN
Master SIN/
Slave SOUT
PCSx/SS
t
CSC
MSB first (LSBFE = 0):
LSB first (LSBFE = 1):
t = PCS to SCK delay
CSC
t = After SCK delay
ASC
t = Delay after Transfer (minimum CS negation time)
DT
The master initiates the transfer by asserting the PCS signal to the slave.
After the t
time places valid data on the master SOUT pin. The slave responds to the first SCK edge by
placing its first data bit on its slave SOUT pin.
At the second edge of the SCK the master and slave sample their SIN pins.
For the rest of the frame the master and the slave change the data on their SOUT pins on
the odd-numbered clock edges and sample their SIN pins on the even-numbered clock
edges.
After the last clock edge occurs a delay of t
PCS signal. A delay of t
master.
46.5.6.3 Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 0)
In this Modified Transfer Format both the master and the slave sample later in the SCK
period than in Classic SPI mode to allow the logic to tolerate more delays in device pads
and board traces. These delays become a more significant fraction of the SCK period as the
SCK period decreases with increasing baud rates.
The master and the slave place data on the SOUT pins at the assertion of the PCS signal.
After the PCS to SCK delay has elapsed the first SCK edge is generated. The slave
samples the master SOUT signal on every odd numbered SCK edge. The DSPI in the slave
1 2 3 4 5
MSB Bit 6 Bit 5
LSB Bit 1 Bit 2
delay has elapsed, the master generates the first SCK edge and at the same
CSC
is inserted before a new frame transfer can be initiated by the
DT
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
6 7 8 9 10 11 12 13 14
Bit 4 Bit 3
Bit 3 Bit 4
is inserted before the master negates the
ASC
15 16
t
ASC
Bit 2 Bit 1 LSB
Bit 5 Bit 6 MSB
t
DT
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