Memory Map And Register Definition - STMicroelectronics SPC572L series Reference Manual

RM0400
22.5

Memory map and register definition

This section provides the memory map and detailed descriptions of all registers for
configuring the PLLs.
22.5.1 Memory map
Table 220
address. All registers can be accessed using 8-bit, 16-bit or 32-bit addressing.
Offset
(hex)
0000 PLLCR — PLL Control Register
0004 PLLSR — PLL Status Register
0008 PLLDV — PLL Divider Register
000C–0012 Reserved
0014–001C Reserved
0018 Reserved
0020–0030 Reserved
0034–0038 Reserved
See the "Clocking" chapter for default reset values.
1.
22.5.2 Register descriptions
Some of the register reset values are specifically configured for each unique device by
external configuration signals or parameters.
shows the memory map. Addresses are given as offsets from the module base
Table 220. PLL Digital Interface memory map
Register
DocID027809 Rev 4
PLL Digital Interface (PLLDIG)
Reset Value
Access
(hex)
R/W 0000_0000h
R/W 0000_0000h
zzzz_z0zzh
R/W
(1)
— —
— —
— —
— —
— —
Section/Page
on page 480
on page 481
on page 482
—
—
—
—
—
479/2058
485