Mib Control Register (Mibc) - STMicroelectronics SPC572L series Reference Manual

Fast Ethernet Controller (FEC)
Internal FEC clock frequency
40 MHz
50 MHz
66 MHz
80 MHz
83 MHz
48.4.8

MIB Control Register (MIBC)

The MIBC is a read/write register controlling and observing the state of the MIB block. User
software accesses this register if there is a need to disable the MIB block operation. For
example, to clear all MIB counters in RAM:
1. Disable the MIB block
2. Clear all the MIB RAM locations
3. Enable the MIB block
The MIB_DIS bit is reset to 1. See the memory map for the locations of the MIB counters.
Offset: 064h
0 1 2 3
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
MIB_DIS If MIB_DIS = 1, the MIB logic halts and not update any MIB counters.
MIB_IDLE If MIB_IDLE = 1, the MIB block is not currently updating any MIB counters.
48.4.9 Receive Control Register (RCR)
RCR controls the operational mode of the receive block and must be written only when
ECR[ETHER_EN] is cleared (initialization time).
1310/2058
Table 706. Programming examples for MSCR(Continued)
MSCR[MII_SPEED]
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 697. MIB Control Register (MIBC)
Table 707. MIBC field descriptions
DocID027809 Rev 4
8h
Ah
Eh
10h
10h
Description
RM0400
FEC_MDC frequency
2.50 MHz
2.50 MHz
2.36 MHz
2.50 MHz
2.59 MHz
Access: User read/write