Table 222. Pllsr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Loss of lock reset enable. The PLLCR[LOLRE] bit determines whether system reset is asserted or
not upon a loss of lock indication from PLL. If both PLL0CR[LOLRE] = 1 and PLL0CR[LOLIE] = 1,
29
PLL0CR[LOLRE] has precedence and the device asserts reset with the interrupt not being taken.
LOLRE
0 Ignore loss of lock. Reset not asserted.
1 Assert reset on loss of lock when operating in normal mode.
30 Reserved
31 Reserved
22.5.2.2 PLL Status Register (PLLSR)
Offset: 0004h
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
1. This field is reserved, read only.
Field
0:23 Reserved
External Power Down Cycle Complete indication interrupt flag. This bit indicates that the external power
down of the PLL is complete (for example, PLLs are powered down and then powered up). User must
24
write 1 to clear this bit.
EXTPDF
0 PLLs not power cycled. Interrupt not requested
1 PLLs power down cycle is complete. Interrupt is requested
25 Reserved
26 Reserved
27 Reserved
Loss of lock flag. This bit provides the interrupt flag for the loss of lock condition. Software must write 1
to LOLF to clear it, writing 0 has no effect. The flag is set when the PLL loses lock or when the
28 divider/modulation registers are changed on the fly. This flag bit is sticky in the sense that if lock is
reacquired, the bit will remain set until cleared by either writing 1 or asserting reset.
LOLF
0 No loss of lock detected. Interrupt service not requested.
1 Loss of lock detected. Interrupt service requested.
Table 221. PLLCR field descriptions(Continued)
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 171. PLL Status Register (PLLSR)

Table 222. PLLSR field descriptions

DocID027809 Rev 4
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0
w1c
0 0 0 —
Description
PLL Digital Interface (PLLDIG)
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0
(1)
*
w1c
0 — 0 0
14 15
0 0
0 0
30 31
0
(1)
*
0 0
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