Mii Speed Control Register (Mscr) - STMicroelectronics SPC572L series Reference Manual

RM0400
48.4.7

MII Speed Control Register (MSCR)

The MSCR:
•
Provides control of the MII clock (FEC_MDC pin) frequency
•
Allows a preamble drop on the MII management frame
Offset: 044h
0 1 2
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
Setting this bit causes the preamble (32 ones) not to be prepended to the MII management frame.
DIS_PRE The MII standard allows the preamble to be dropped if the attached PHY device(s) does not require
it.
Controls the frequency of the MII management interface clock (FEC_MDC) relative to the internal
bus clock. A value of 0 in this field turns off the FEC_MDC and leaves it in low voltage state. Any
MII_SPEED
non-zero value results in the FEC_MDC frequency of 1/(MII_SPEED × 2) of the internal bus
frequency.
The MII_SPEED field must be programmed with a value to provide an FEC_MDC frequency
of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The
MII_SPEED must be set to a non-zero value to source a read or write management frame.
After the management frame is complete, the MSCR register may optionally be set to 0 to
turn off the FEC_MDC. The FEC_MDC generated has a 50% duty cycle except when
MII_SPEED changes during operation (change takes effect following a rising or falling edge
of FEC_MDC).
If the internal bus clock is 25 MHz, programming this register to 0000_0005h results in an
FEC_MDC as stated the equation below.
Equation 31
Table 706
frequency.
Internal FEC clock frequency
25 MHz
33 MHz
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 696. MII Speed Control Register (MSCR)
Table 705. MSCR field descriptions
shows optimum values for MII_SPEED as a function of internal bus clock
Table 706. Programming examples for MSCR
Description
1
× ------------
25 MHz = 2.5 MHz
×
5 2
MSCR[MII_SPEED]
5h
7h
DocID027809 Rev 4
Fast Ethernet Controller (FEC)
Access: User read/write
MII_SPEED
FEC_MDC frequency
2.50 MHz
2.36 MHz
0
1309/2058
1358