Figure 44. E200Z215An3 Supervisor Mode Programmer's Model Sprs - STMicroelectronics SPC572L series Reference Manual

RM0400
General Registers
Condition
CR
Count Register
CTR
SPR
Link
LR SPR 8
XER
XER SPR 1
Processor Control Registers
Machine State
MSR
Processor
PVR
SPR 287
Processor ID
PIR SPR 286
Debug Registers
Control
Debug
SPR
DBCR0
308
DBCR1
SPR
DBCR2
)2
309
(DBCR3
1
SPR
DBCR4
1
310
DBCR5
1
SPR
DBCR6
1
561
DBCR7
1
SPR
DBCR8
563
EDBRAC0
1
SPR
1
564
DEVENT
1
SPR
DDAM
603
1. These core-specific registers may not be supported by other PowerPC processors.
2. Not implemented.

Figure 44. e200z215An3 Supervisor Mode Programmer's Model SPRs

SUPERVISOR Mode Programmer's Model SPRs
General-Purpose
Registers
GPR0
GPR1
Hardware
Implementation
1
Dependent
HID0 SPR
1
System Version
SVR
SPR 1023
Instruction Address
Compare
SPR
IAC1
312
IAC2
SPR
IAC3
313
IAC4
SPR
IAC5
314
IAC6
SPR
IAC7
315
IAC8
Data Value
DVC1U, DVC1
SPR 601, 318
SPR 602, 319
DVC2U, DVC2
Exception Handling/Control Registers
SPR General
SPRG0 SPR
SPRG1 272
SPRG2 SPR
SPRG3 273
User SPR General
USPRG0 SPR
(VR-
BTB Register
1
BTB Control
SPR
BUCSR
EFPU Registers
EFPU APU Status
and
Control Register
SPEF- SPR
Data Address
Compare
DAC1 SPR
DAC2 316
DAC3 SPR
DAC4 317
SPR
Debug Status
592
DBSR SPR 304
DDEAR SPR 600
NEXUS3 Register
1
Nexus PID
SPR 517
NPIDR
DocID027809 Rev 4
Core e200z215An3 description
Save and
Restore
Interrupt Vector Prefix
IVPR
SRR0 SPR 26
SRR1 SPR 27
CSRR0 SPR 58
CSRR1 SPR 59
DSRR0 SPR 574
DSRR1 SPR 575
MCSRR0 SPR 570
MCSRR1 SPR 571
Machine Check
Exception Syndrome
Syndrome Register
Register
ESR SPR
MCSR
Data Exception
Machine Check
DEAR SPR
Address
MCAR
Memory Management Registers
Process ID Configuration
(Read-only)
PID0 SPR 48
MMUCFG
Cache Registers
Cache
Configuration
(Read-only)
L1CFG0 SPR 515
L1CFG1 SPR 516
Local Memory Con-
(Read-only)
DMEMCFG0 SPR 694
SPR 695
IMEMCFG
SPR
572
SPR
SPR 573
SPR
1015
261/2058
282