Table 60. Protected Plldig Registers - STMicroelectronics SPC572L series Reference Manual

Device configuration
Register
RES_VD7
REE_VD9
RES_VD9
REE_VD10
RES_VD10
REE_TD
RES_TD
CTL_TD
MREG_CTRL
VD_UTST
ADC_CH
6.7.12.4 PLL Digital Interface (PLLDIG) protected registers
Table 60
Register
PLL0CR — PLL0 Control
Register
PLL0DIVR — PLL0 Divider
Register
6.7.12.5 Oscillator Digital Interface (XOSC) protected registers
Table 61
Register
OSC_CTL
6.7.12.6 Mode Entry (MC_ME) protected registers
Table 62
176/2058
Table 59. Protected PMC_dig registers(Continued)
Register size (bits)
32
32
32
32
32
32
32
32
8
8
8
lists the PLLDIG registers that can be protected.

Table 60. Protected PLLDIG registers

Register size (bits)
32
32
lists the XOSC registers that can be protected.
Table 61. Protected XOSC registers
Register size (bits)
32
lists the MC_ME registers that can be protected.
DocID027809 Rev 4
Offset from module
base address
0x0078
0x0094
0x098
0x0A4
0x0A8
0x0304
0x0308
0x030C
0x240
0x340
0x344
Offset from module
base address
0x0000
0x0008
Offset from module
base address
0x0000
RM0400
Protected size (bits)
32
32
32
32
32
32
32
32
8
8
8
Protected size (bits)
8
32
Protected size (bits)
32