Low Voltage Detection (Lvd) - STMicroelectronics SPC572L series Reference Manual

Power management
Figure 37. Internal LVD and HVD in configuration example during power-up
EXTERNAL
System kept
REGULATOR
under Reset
V
(Example)
+11%
1.388V
+7%
1.338V
+2%
1.275V
Static
1.250V
regulator
1.225V
-2%
1.200V
-4%
1.200V
1.188V
-5%
External
LVD
1.138V
-9%
Power-ON
9.5.3

Low Voltage Detection (LVD)

Internal Voltage Detector circuits monitor the voltage on assigned supplies and assert resets
or interrupts when limits are breached. The voltage detectors support hysteresis in the
falling and rising trip points.
9.5.3.1 LVD implementation
•
All LVDs are capable of generating an RGM event, with the following exceptions:
–
–
•
All LVDs configured for reset generation can cause functional or destructive resets.
MC_RGM cannot exit PHASE0 until all destructive reset conditions are cleared.
•
The appropriate bits in the PMC registers are set by LVD events.
•
Modification of LVD and HVD control registers is subject to procedures in
Register Protection
•
REE DCF records configure LVDs/HVDs to a RESET event. This is a write-once
mechanism managed by SSCM during device initialization. When a REE DCF record
configures a RESET event, it cannot be changed until the next RESET event.
Note: Details regarding configurable LVDs/HVDs are provided in
• The external PORST pin is driven low when a destructive-reset-enabled LVD is
triggered.
226/2058
Device Initialization
30mV internal drop
1.170V
1.080V
Power OK
Trimming not applied
LVD270 monitor high voltage supply input and always generate a reset when
triggered (can only be disabled for test purposes).
LVD098 monitor the internal core voltage and always generate a reset when
triggered (cannot be disabled). LVD098 is integral to POR management.
(REG_PROT).
DocID027809 Rev 4
Operating mode
VDD_LV
1.200V
60mV internal drop
1.140V
1.2V internal LVDs enabled
(reset event generated)
Power OK
Trimming applied
Table 74
RM0400
DEVICE
Out of SoC
specification
+5%
V core
DD
(MCU)
-4%
Internal
LVDs
Out of SoC
t
specification
Chapter 67: