Table 790. Gbl_Ctrl Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
0
R
W
Reset 0
8
R
W
Reset 0
16
R
W
Reset 0
24
R
W
Reset 0
Field
Time Stamp Prescaler Value. Value in number of clock cycles of high frequency receiver clock set in
order to obtain a clock frequency for the time stamp counter block.
0 – Prescaler Bypassed. Time Stamp Clock = High Frequency Receiver Clock
1 to 255 – Value set by user software to obtain a clock period of at least 1us for the time stamp
0:7
counter.
TSPRSC
If the high frequency clock input is 75 MHz, then the value set in this field would be 0x4B (or 75) to
obtain a 1µs clock.
Note: Since the time stamp clock is common for all channels, the timestamp clock frequency must be
at least twice the fastest receiver channel in the application. This is to ensure that the time stamp
clock is fast enough to show change in timestamp from message to message.
8:15 Reserved. Read returns zero
16:21 Reserved. Read returns zero
Fast Message DMA Underflow Interrupt Enable: Enables interrupt assertion when there is an
underflow condition on Fast Message DMA registers. Default value is 0.
22
FMDUIE
0 – Interrupt is disabled
1 – Interrupt is enabled
Address Offset = 0x0000
1 2
0 0
9 10
0 0
17 18
0 0
25 26
FAST_CLR
0 0
Figure 778. Global Control Register (GBL_CTRL)

Table 790. GBL_CTRL field descriptions

DocID027809 Rev 4
3 4
TSPRSC
0 0
11 12
0 0
19 20
0 0
27 28
DBG_FRZ
1 0
Description
SENT Receiver (SRX)
Access: RW
5 6
0 0
13 14
0 0
21 22
FMDUIE SMDUIE
0 0
29 30
SENT_EN
0 0
1367/2058
7
0
15
0
23
0
31
0
1410