Table 664. Picr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communications
Field
0-14 Reserved
Ping Response Frame Request. This bit is set to initiate the transfer of Ping response frame.
15 Cleared after transmission of Ping response frame.
PNGREQ 1 Ping response frame transmission request is queued
0 No pending Ping response frame transmission request
Ping Response Enable. Defines when ping response should be automatically sent on reception of
16 Ping ICLC frame from LFAST master
PNGAUTO 0 Ping response should not be automatically sent.
1 Ping response should be automatically sent.
17-23 Reserved
LFAST Slave: Defines the LFAST slaves ping reply frame payload content.
24-31
LFAST Master: Defines the expected payload of ping response frame. Used for comparison with ping
PNGPYLD
frame received.
47.6.2.10 Rx FIFO CTS Control Register (RFCR)
Offset:
002Ch
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
1
Only writable when MCR[DRFEN] = 0.
Field
0-9 Reserved
10-15
Rx FIFO Maximum Threshold. Defines the condition for CTS bit of frames to be negated.
RCTSMX
16-25 Reserved
26-31
Rx FIFO Minimum Threshold. Defines the condition for CTS bit of frames to be set.
RCTSMN
1238/2058

Table 664. PICR field descriptions

2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 650. Rx FIFO CTS Control Register (RFCR)
Table 665. RFCR field descriptions
DocID027809 Rev 4
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Description
Access: User read/write
10 11 12 13
1
RCTSMX
0 0 1 1
26 27 28 29
1
RCTSMN
0 0 1 0
14 15
1 1
30 31
0 1